FPGA market brochure

Executive summary

The PLD market
Overview of the PLD market
Comparison between the FPGA, ASSP and ASIC markets
Revenue breakdown by vendor over the period 2006 – 2009
FPGA revenue
FPGA market segmentation
LE comparison of high performance FPGAs
LE comparison of low-cost FPGAs

Competition in the FPGA market
Overview of the market dynamics
Anatomy of an FPGA
Design Tools
Key customer “care abouts”
Customers for high performance FPGAs
Customers for low-cost FPGAs
Overview of the existing vendors
High Performance Status Quo
The Low-Cost Market
FPGA Costs and Prices
FPGA pricing strategies
Estimate of ASP and shipped quantities by family

Strategies for minimising FPGA costs
RFQ considerations
Device selection
Design Partitioning
Package Options
External IP
Power supply and external components
Design Techniques to reduce device costs
Floor planning
P and R Settings
Synthesis Tools
Design Techniques

FPGA vendor profiles
Xilinx Inc. (NASDAC- XLNX)
Xilinx high performance families
Xilinx low-cost families
Altera Corp. (NASDAC- ALTR)
Altera high performance families
Altera low-cost families
Actel Corp. (NASDAC- ACTL)
Lattice Semiconductor Corp. (NASDAC- LSCC)
QuickLogic Corp. (NASDAC- QUIK)
Atmel Corp.
Recent market entrants
Abound Logic Inc.
Achronix Semiconductor
SiliconBlue Technologies Corp.
New product possibilities from existing vendors
Known “stealth mode” companies
NuPGA
Silicon Basis
Tabula
Tier Logic
Potential for a new vendor to break into the FPGA market
Possible scenarios
Minimum requirements for start-up success

Applications for FPGAs
Overview of applications
Estimated power consumption of FPGAs
Aerospace and defence
Automotive
AVB market
Consumer
Data processing and storage
Industrial, scientific and medical
Wired communications
Wireless communications
Application areas for a new market entrant to consider
Targeting a market sector
ASIC, ASSP and DSP market overlap with the FPGA space
HardCopy
EasyPath
AKYA
Cswitch
Cypress
eASIC
Multi-Core and Many-Core products
picoChip, TI and Array-of-processor products
XMOS
Tilera
Element CXI

Appendix
Product categories and technology
High performance family resources tables
Low-cost family resources tables
Glossary of terms
Data sources
Author background
Methodology used
Legal notices

LIST OF FIGURES
Figure 1. Quarterly PLD market share by vendors
Figure 2. Quarterly CPLD revenue by major vendors
Figure 3. Quarterly FPGA market share by PLD vendors
Figure 4. Logic element count for high performance families
Figure 5. Low-cost families that extend above 100k Logic Elements
Figure 6. Low-cost FPGA families below 100k Logic Elements
Figure 7. Revenue growth of Altera and Xilinx
Figure 9. Revenue comparison between leading PLD companies and the total semiconductor market (2001 - 2008)
Figure 10. ITRS road map for low power ASIC technology
Figure 11. ITRS road map for ASIC technology power supply voltage
Figure 12. Typical floor plan of an FPGA
Figure 13. Simplified diagram of a Logic Element
Figure 14. Simplified diagram of an Input / Output block
Figure 15. DSP hard macro taken from the Virtex-5 FPGA data sheet
Figure 16. An example of the complexity of high performance FPGAs (Stratix IV GX)
Figure 17. Typical top level design flow
Figure 18. Typical elements of an FPGA design flow
Figure 19. Relative positioning of high performance and low-cost FPGAs
Figure 20. Largest FPGA announced (by equivalent 4-input Logic Elements - LEs)
Figure 21. An example of a PIC Endpoint integrating PHY, DLL and Transaction layers
Figure 22. Staggered bond pads
Figure 23. Possible partitions to achieve a lower cost solution
Figure 24. Floor planner screen showing major blocks and interconnections
Figure 25. Achronix Speedster FPGAs use asynchronous signalling internally to reduce delays
Figure 26. ITRS projections of leakage current
Figure 27. TSMC wafer revenues from 65-nm (and recently 40-nm) shipments
Figure 28. TSMC revenue in Q2CY09 by technology
Figure 29. World-wide fab capital expenditure (CAPEX)
Figure 30. A redundancy scheme to increase yields of large die and high defect densities
Figure 31. PLD market by end applications Q3CY09
Figure 32. Openness to novel FPGA products from new vendors
Figure 33. Cypress PSoC architecture with embedded ARM Cortex M3 processor
Figure 34. Independent benchmark results for OFDM system
Figure 35. XMOS quad Xcore device
Figure 36. XMOS multi-thread operation
Figure 37. XMOS tool flow

LIST OF TABLES
Table 1. Quarterly PLD sales revenue ($M) by vendors
Table 2. Quarterly PLD market share by vendors
Table 3. CPLD sales revenue ($M) by vendors
Table 4. Quarterly FPGA revenue results
Table 5. Altera shipments by category
Table 6. Xilinx shipments by category
Table 7. Geographic shipments by Altera and Xilinx
Table 8. Vendor direct headcount
Table 9. List price for Xilinx software support packages
Table 10. Existing and announced FPGA technologies
Table 11. List price for Xilinx sample quantities of Spartan-6
Table 12. Published low-cost FPGA prices
Table 13. Published high performance FPGA prices
Table 14. ASP and unit volumes for FPGA shipments in 2008
Table 15. Xilinx shipments by end market (* with judgements on some categories)
Table 16. Altera shipments by end market (* with judgements on some categories)
Table 17. Actel shipments by end market
Table 18. Lattice shipments by end market
Table 19. QuickLogic shipments by end market
Table 20. End market PLD shipments for Q3CY09.
Table 21. End market PLD shipments by revenue for Q3CY09
Table 22. End market for low-cost FPGA shipments for Q3CY09
Table 23. End market high performance FPGA shipments for Q3CY09
Table 24. End market annual FPGA shipments for last four quarters
Table 25. Vendor products categorised as high performance showing technologies and supply voltages
Table 26. Vendor products categorised as low-cost showing technologies and supply voltages
Table 27. Altera high performance families
Table 28. Altera high performance family special features
Table 29. Xilinx high performance families
Table 30. Xilinx high performance family special features
Table 31. Abound high performance family
Table 32. Abound high performance family special features
Table 33. Achronix high performance family
Table 34. Achronix high performance family special features
Table 35. Altera mid range and low-cost families
Table 36. Altera mid range and low-cost families special features
Table 37. Xilinx low-cost families
Table 38. Xilinx low-cost families special features
Table 39. Actel low-cost families
Table 40. Actel low-cost families special features
Table 41. Lattice low-cost families
Table 42. Lattice low-cost families special features
Table 43. QuickLogic low-cost families
Table 44. QuickLogic low-cost families special features
Table 45. SiliconBlue low-cost family
Table 46. SiliconBlue low-cost family special features




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